1. Field of the Invention
The present invention relates to the field of integrated circuit fabrication, and more specifically to a method for forming an interface free layer of silicon on a substrate of monocrystalline silicon.
2. Description of Related Art
Integrated circuit production often requires the flexibility of adding a semiconducting or insulating layer on top of a partially formed circuit. Particularly, a layer of silicon deposited on a substrate of monocrystalline silicon (or monosilicon) is typically used as a source of dopant (or impurities) for the substrate and/or as a contact for connecting an underlying region of the substrate with the external environment.
A solution known to one of ordinary skill in the art and extensively employed in several applications includes forming a layer of polycrystalline silicon (or polysilicon) on the monosilicon substrate. The polysilicon layer is obtained with a Chemical Vapor Deposition (CVD) process, which is carried out at a low temperature (about 600-700xc2x0 C.).
For example, the CVD process is employed for manufacturing bipolar transistors for high speed switching and high frequency analog applications. The most commonly used bipolar transistors have vertically aligned emitter, base and collector regions. The bipolar transistors show a shallow architecture, with a very thin base region that speeds up their switching. In this type of device, such as the devices produced using Double Polysilicon Self Aligned (DPSA) technology, the collector and base regions are formed in a monosilicon substrate. The emitter region consists of a polysilicon layer that is deposited over the base region. The use of a low temperature for the deposition of the polysilicon layer reduces any undesired dopant diffusion from the base region, thereby avoiding an increase in its width. This aspect in particular is extremely important in the manufacturing of Heterojunction Bipolar Transistors (HBTs), wherein germanium is added to the (silicon) base region to improve the speed of the devices. In this case, any prolonged heating of the devices at high temperature must be avoided in order to prevent the formation of lattice defects (attributed to the difference in lattice constants between silicon and germanium) and to prevent dopants from diffusing from their desired position.
The polysilicon emitter described above, however, has a major drawback, especially for advanced ultra-shallow devices. The polysilicon emitter causes an increased recombination of minority charges during operation of the transistor. This phenomenon reduces the gain of the transistor and increases its noise.
Several techniques have been proposed for controlling an interface between the monosilicon substrate and the emitter region, from both a material and an electrical standpoint. One known solution involves creating interstitial defects on a surface of the monosilicon substrate. A layer of silicon is then deposited on the substrate at low temperature. The layer has a monocrystalline structure on its lower side, with crystallographic axes different from the axes of the substrate, and a polycrystalline or amorphous structure on its upper side.
Another solution involves of depositing a thin layer of amorphous silicon in-situ doped on the substrate. A capping layer of polysilicon is then deposited on the layer of amorphous silicon. The two layers are then subjected to a prolonged heating (of several hours, for example) at low temperature, in order to re-crystallize the layer of amorphous silicon into a single crystal by Solid Phase Epitaxy (SPE).
None of the known solutions, however, are completely satisfactory. For example, the interface between the monosilicon substrate and the emitter region causes dopant segregation from the substrate to the interface, and then into the emitter region. Moreover, the interface increases the electrical resistance of the emitter region, which limits the maximum current rating of the transistor. This results in degradation of transistor characteristics and yield.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a method of forming an interface free layer of silicon on a substrate of monocrystalline silicon.
One embodiment of the present invention provides a method for forming an interface free layer of silicon on a substrate of monocrystalline silicon. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided and a silicon layer in-situ doped is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700xc2x0 C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through a part of the polycrystalline portion of the silicon layer.
Another embodiment of the present invention provides a method for manufacturing a bipolar transistor. According to the method, a substrate of monocrystalline silicon having a surface substantially free of oxide is provided. The substrate includes a collector region of a first conductivity type and a base region of a second conductivity type. A silicon layer in-situ doped with the first conductivity type is deposited on the surface of the substrate in an oxygen-free environment and at a temperature below 700xc2x0 C. so as to produce a monocrystalline portion of the silicon layer adjacent to the substrate and a polycrystalline portion of the silicon layer spaced apart from the substrate. The silicon layer is heated so as to grow the monocrystalline portion of the silicon layer through part of the polycrystalline portion of the silicon layer, the monocrystalline portion of the silicon layer defining an emitter region and the polycrystalline portion defining a contact region for the emitter region.
Other objects, features and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.